测试
SN65HVD230SN65HVD231
SN65HVD232
SLOS346G – MARCH 2001 – REVISED JUNE 2002
3.3-V CAN TRANSCEIVERS
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FEATURES
Operates With a 3.3-V Supply
Low Power Replacement for the PCA82C250
Footprint
Bus/Pin ESD Protection Exceeds 16 kV HBM
High Input Impedance Allows for 120 Nodes
on a Bus
Controlled Driver Output Transition Times for
Improved Signal Quality on the SN65HVD230
and SN65HVD231
Unpowered Node Does Not Disturb the Bus
Compatible With the Requirements of the
ISO 11898 Standard
Low-Current SN65HVD230 Standby Mode
370 μA Typical
Low-Current SN65HVD231 Sleep Mode
40 nA Typical
Designed for Signaling Rates† up to
1 Megabit/Second (Mbps)
Thermal Shutdown Protection
Open-Circuit Fail-Safe Design
Glitch-Free Power-Up and Power-Down
Protection for Hot-Plugging Applications
APPLICATIONS
Motor Control
Industrial Automation
Basestation Control and Status
Robotics
Automotive
UPS Control
LOGIC DIAGRAM (POSITIVE LOGIC)
CANL
CANH
R
D 1
4
7
6
SN65HVD230, SN65HVD231
Logic Diagram (Positive Logic)
RS
8
Vref
3 5
VCC
CANL
CANH
R
D 1
4
7
6
SN65HVD232
Logic Diagram (Positive Logic)
† The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second).
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 2002, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
D
GND
VCC
R
RS
CANH
CANL
Vref
SN65HVD230D (Marked as VP230)
SN65HVD231D (Marked as VP231)
(TOP VIEW)
1
2
3
4
8
7
6
5
NC – No internal connection
D
GND
VCC
R
NC
CANH
CANL
NC
SN65HVD232D (Marked as VP232)
(TOP VIEW)
1
2
3
4
8
7
6
5
TMS320Lx240x is a trademark of Texas Instruments.
SN65HVD230
SN65HVD231
SN65HVD232
SLOS346G – MARCH 2001 – REVISED JUNE 2002
2 www.ti.com
DESCRIPTION
The SN65HVD230, SN65HVD231, and SN65HVD232 controller area network (CAN) transceivers are designed
for use with the Texas Instruments TMS320Lx240x 3.3-V DSPs with CAN controllers, or with equivalent
devices. They are intended for use in applications employing the CAN serial communication physical layer in
accordance with the ISO 11898 standard. Each CAN transceiver is designed to provide differential transmit
capability to the bus and differential receive capability to a CAN controller at speeds up to 1 Mbps.
Designed for operation in especially-harsh environments, these devices feature cross-wire protection,
loss-of-ground and overvoltage protection, overtemperature protection, as well as wide common-mode range.
The transceiver interfaces the single-ended CAN controller with the differential CAN bus found in industrial,
building automation, and automotive applications. It operates over a –2-V to 7-V common-mode range on the
bus, and it can withstand common-mode transients of ±25 V.
On the SN65HVD230 and SN65HVD231, pin 8 provides three different modes of operation: high-speed, slope
control, and low-power modes. The high-speed mode of operation is selected by connecting pin 8 to ground,
allowing the transmitter output transistors to switch on and off as fast as possible with no limitation on the rise
and fall slopes. The rise and fall slopes can be adjusted by connecting a resistor to ground at pin 8, since the
slope is proportional to the pin’s output current. This slope control is implemented with external resistor values
of 10 kΩ, to achieve a 15-V/μs slew rate, to 100 kΩ, to achieve a 2-V/μs slew rate. See the Application
Information section of this data sheet.
The circuit of the SN65HVD230 enters a low-current standby mode during which the driver is switched off and
the receiver remains active if a high logic level is applied to pin 8. The DSP controller reverses this low-current
standby mode when a dominant state (bus differential voltage > 900 mV typical) occurs on the bus.
The unique difference between the SN65HVD230 and the SN65HVD231 is that both the driver and the receiver
are switched off in the SN65HVD231 when a high logic level is applied to pin 8 and remain in this sleep mode
until the circuit is reactivated by a low logic level on pin 8.
The Vref pin 5 on the SN65HVD230 and SN65HVD231 is available as a VCC/2 voltage reference.
The SN65HVD232 is a basic CAN transceiver with no added options; pins 5 and 8 are NC, no connection.
AVAILABLE OPTIONS
PART NUMBER
LOW
POWER MODE
INTEGRATED SLOPE
CONTROL Vref PIN TA MARKED AS:
SN65HVD230 Standby mode Yes Yes VP230
SN65HVD231 Sleep mode Yes Yes –40°C to 85°C
VP231
SN65HVD232 No standby or sleep mode No No
40 85 VP232
SN65HVD230
SN65HVD231
SN65HVD232
SLOS346G – MARCH 2001 – REVISED JUNE 2002
www.ti.com 3
Function Tables
DRIVER (SN65HVD230, SN65HVD231)
INPUT D R
OUTPUTS
RS BUS STATE
CANH CANL
L
V 12V
H L Dominant
H
V(Rs) < 1.2 V
Z Z Recessive
Open X Z Z Recessive
X V(Rs) > 0.75 VCC Z Z Recessive
H = high level; L = low level; X = irrelevant; ? = indeterminate; Z = high impedance
DRIVER (SN65HVD232)
INPUT D
OUTPUTS
BUS STATE
CANH CANL
L H L Dominant
H Z Z Recessive
Open Z Z Recessive
H = high level; L = low level; Z = high impedance
RECEIVER (SN65HVD230)
DIFFERENTIAL INPUTS RS OUTPUT R
VID ≥ 0.9 V X L
0.5 V < VID < 0.9 V X ?
VID ≤ 0.5 V X H
Open X H
H = high level; L = low level; X = irrelevant; ? = indeterminate
RECEIVER (SN65HVD231)
DIFFERENTIAL INPUTS RS OUTPUT R
VID ≥ 0.9 V L
0.5 V < VID < 0.9 V V(< 1.2 V
?
VID ≤ 0.5 V
Rs) H
X V(Rs) > 0.75 VCC H
X 1.2 V < V(Rs) < 0.75 VCC ?
Open X H
H = high level; L = low level; X = irrelevant; ? = indeterminate
RECEIVER (SN65HVD232)
DIFFERENTIAL INPUTS OUTPUT R
VID ≥ 0.9 V L
0.5 V < VID < 0.9 V ?
VID ≤ 0.5 V H
Open H
H = high level; L = low level; X = irrelevant;
? = indeterminate
SN65HVD230
SN65HVD231
SN65HVD232
SLOS346G – MARCH 2001 – REVISED JUNE 2002
4 www.ti.com
Function Tables (Continued)
TRANSCEIVER MODES (SN65HVD230, SN65HVD231)
V(Rs) OPERATING MODE
V(Rs) > 0.75 VCC Standby
10 kΩ to 100 kΩ to ground Slope control
V(Rs) < 1 V High speed (no slope control)
Terminal Functions
SN65HVD230, SN65HVD231
TERMINAL
DESCRIPTION
NAME NO.
CANL 6 Low bus output
CANH 7 High bus output
D 1 Driver input
GND 2 Ground
R 4 Receiver output
RS 8 Standby/slope control
VCC 3 Supply voltage
Vref 5 Reference output
SN65HVD232
TERMINAL
DESCRIPTION
NAME NO.
CANL 6 Low bus output
CANH 7 High bus output
D 1 Driver input
GND 2 Ground
NC 5, 8 No connection
R 4 Receiver output
VCC 3 Supply voltage
SN65HVD230
SN65HVD231
SN65HVD232
SLOS346G – MARCH 2001 – REVISED JUNE 2002
www.ti.com 5
equivalent input and output schematic diagrams
VCC
D Input
1 kΩ
9 V
Input
100 kΩ
VCC
Output
16 V
CANH and CANL Outputs
20 V
VCC
5 Ω
9 V
Output
R Output
VCC
Input
16 V
CANH and CANL Inputs
20 V
110 kΩ
45 kΩ
9 kΩ
9 kΩ
SN65HVD230
SN65HVD231
SN65HVD232
SLOS346G – MARCH 2001 – REVISED JUNE 2002
6 www.ti.com
absolute maximum ratings over operating free-air temperature (see Note 1) (unless otherwise
noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 6 V
Voltage range at any bus terminal (CANH or CANL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –4 V to 16 V
Voltage input range, transient pulse, CANH and CANL, through 100 Ω (see Figure 7) . . . . . . . . . . . . –25 V to 25 V
Input voltage range, VI (D or R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Electrostatic discharge: Human body model (see Note 2) CANH, CANL and GND . . . . . . . . . . . . . . . . . . 16 kV
All Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 kV
Charged-device model (see Note 3) All pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 kV
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating table
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
2. Tested in accordance with JEDEC Standard 22, Test Method A114-A.
3. Tested in accordance with JEDEC Standard 22, Test Method C101.
DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR‡
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
D 725 mW 5.8 mW/°C 464 mW 377 mW
‡ This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
recommended operating conditions
PARAMETER MIN NOM MAX UNIT
Supply voltage, VCC 3 3.6 V
Voltage at any bus terminal (common mode) VIC –2§ 7 V
Voltage at any bus terminal (separately) VI –2.5 7.5 V
High-level input voltage, VIH D, R 2 V
Low-level input voltage, VIL D, R 0.8 V
Differential input voltage, VID (see Figure 5) –6 6 V
Input voltage, V(Rs) 0 VCC V
Input voltage for standby or sleep, V(Rs) 0.75 VCC VCC V
Wave-shaping resistance, Rs 0 100 kΩ
High level output current I
Driver –40
High-current, IOH mA
Receiver –8
Low level output current I
Driver 48
Low-current, IOL mA
Receiver 8
Operating free-air temperature, TA –40 85 °C
§ The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
SN65HVD230
SN65HVD231
SN65HVD232
SLOS346G – MARCH 2001 – REVISED JUNE 2002
www.ti.com 7
driver electrical characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT
V Dominant
VI = 0 V,
CANH 2.45 VCC
VOH
Bus output voltage
See Figure 1 and Figure 3 CANL 0.5 1.25
V
V
Recessive
VI = 3 V,
CANH 2.3
VOL See Figure 1 and Figure 3 CANL 2.3
V Dominant
VI = 0 V, See Figure 1 1.5 2 3
VOD(D) V
Differential output
VI = 0 V, See Figure 2 1.2 2 3
V
out ut
voltage
Recessive
VI = 3 V, See Figure 1 –120 0 12 mV
VOD(R) VI = 3 V, No load –0.5 –0.2 0.05 V
IIH High-level input current VI = 2 V –30 μA
IIL Low-level input current VI = 0.8 V –30 μA
I Short circuit output current
VCANH = –2 V –250 250
IOS Short-mA
VCANL = 7 V –250 250
Co Output capacitance See receiver
Standby SN65HVD230 V(Rs) = VCC 370 600
A
ICC Supply current
Sleep SN65HVD231 V(Rs) = VCC, D at VCC 0.04 1
μA
All devices
Dominant VI = 0 V, No load Dominant 10 17
mA
Recessive VI = VCC, No load Recessive 10 17
† All typical values are at 25°C and with a 3.3-V supply.
driver switching characteristics over recommended operating conditions(unless otherwise noted)
SN65HVD230 and SN65HVD231
PARAMETER
TEST
CONDITIONS MIN TYP MAX UNIT
V(Rs) = 0 V 35 85
tPLH Propagation delay time, low-to-high-level output RS with 10 kΩ to ground 70 125 ns
RS with 100 kΩ to ground 500 870
V(Rs) = 0 V 70 120
tPHL Propagation delay time, high-to-low-level output RS with 10 kΩ to ground 130 180 ns
RS with 100 kΩ to ground 870 1200
V(Rs) = 0 V 35
tsk( p) Pulse skew (|tPHL – tPLH|) RS with 10 kΩ to ground CL = 50 pF,
) 60 ns
RS with 100 kΩ to ground
See Figure 4
370
tr Differential output signal rise time
V 0V
25 50 100 ns
tf Differential output signal fall time
V(Rs) = 0 V
40 55 80 ns
tr Differential output signal rise time
R with 10 kΩ to ground
80 120 160 ns
tf Differential output signal fall time
RS 80 125 150 ns
tr Differential output signal rise time
R with 100 kΩ to ground
600 800 1200 ns
tf Differential output signal fall time
RS 600 825 1000 ns
SN65HVD230
SN65HVD231
SN65HVD232
SLOS346G – MARCH 2001 – REVISED JUNE 2002
8 www.ti.com
driver switching characteristics over recommended operating conditions(unless otherwise noted)
SN65HVD232
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH Propagation delay time, low-to-high-level output 35 85 ns
tPHL Propagation delay time, high-to-low-level output 70 120 ns
tsk(p) Pulse skew (|tP(HL) – tP(LH)|) CL = 50 pF, See Figure 4
35 ns
tr Differential output signal rise time
F, 25 50 100 ns
tf Differential output signal fall time 40 55 80 ns
receiver electrical characteristics over recommended operating conditions (unless otherwise
noted)
PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT
VIT+ Positive-going input threshold voltage
See Table 1
750 900 mV
VIT– Negative-going input threshold voltage
500 650
mV
Vhys Hysteresis voltage (VIT+ – VIT–) 100
VOH High-level output voltage –6 V ≤ VID ≤ 500 mV, IO = –8 mA, See Figure 5 2.4
V
VOL Low-level output voltage 900 mV ≤ VID ≤ 6 V, IO = 8 mA, See Figure 5 0.4
VIH = 7 V 100 250
A
I
VIH = 7 V, VCC = 0 V Other input at 0 V,
100 350
μA
II Bus input current VIH = –2 V
in ut D = 3 V –200 –30
A
VIH = –2 V, VCC = 0 V –100 –20
μA
Ci CANH, CANL input capacitance
Pin-to-ground,
VI = 0.4 sin(4E6πt) + 0.5 V
V(D) = 3 V,
32 pF
Cdiff Differential input capacitance
Pin-to-pin,
VI = 0.4 sin(4E6πt) + 0.5 V
V(D) = 3 V,
16 pF
Rdiff Differential input resistance Pin-to-pin, V(D) = 3 V 40 70 100 kΩ
RI CANH, CANL input resistance 20 35 50 kΩ
ICC Supply current See driver
† All typical values are at 25°C and with a 3.3-V supply.
receiver switching characteristics over recommended operating conditions (unless otherwise
noted)
PARAMETER
TEST
CONDITIONS MIN TYP MAX UNIT
tPLH Propagation delay time, low-to-high-level output 35 50 ns
tPHL Propagation delay time, high-to-low-level output See Figure 6
35 50 ns
tsk(p) Pulse skew (|tP(HL) – tP(LH)|)
10 ns
tr Output signal rise time
See Figure 6
1.5 ns
tf Output signal fall time
1.5 ns
SN65HVD230
SN65HVD231
SN65HVD232
SLOS346G – MARCH 2001 – REVISED JUNE 2002
www.ti.com 9
device switching characteristics over recommended operating conditions (unless otherwise
noted)
PARAMETER
TEST
CONDITIONS MIN TYP MAX UNIT
V(Rs) = 0 V, See Figure 9 70 115
t(LOOP1)
Total loop delay, driver input to receiver
output recessive to dominant
RS with 10 kΩ to ground, See Figure 9 105 175 ns
output, RS with 100 kΩ to ground, See Figure 9 535 920
V(Rs) = 0 V, See Figure 9 100 135
t(Total loop delay, driver input to receiver
output LOOP2)
RS with 10 kΩ to ground, See Figure 9 155 185 ns
output, dominant to recessive
RS with 100 kΩ to ground, See Figure 9 830 990
device control-pin characteristics over recommended operating conditions (unless otherwise
noted)
PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT
t
SN65HVD230 wake-up time from standby mode with RS
See Figure 8
0.55 1.5 μS
t(WAKE) SN65HVD231 wake-up time from sleep mode with RS
3 5 μS
V Reference output voltage
–5 μA < I(Vref) < 5 μA 0.45 VCC 0.55 VCC
Vref V
–50 μA < I(Vref) < 50 μA 0.4 VCC 0.6 VCC
I(Rs) Input current for high-speed V(Rs) < 1 V –450 0 μA
† All typical values are at 25°C and with a 3.3-V supply.
PARAMETER MEASUREMENT INFORMATION
VI
D
IO
IO
VOD
II
0 V or 3 V
CANL
60 Ω
CANH
VCC
Figure 1. Driver Voltage and Current Definitions
±
167 Ω
–2 V ≤ VTEST ≤ 7 V
0 V VOD 60 Ω
167 Ω
Figure 2. Driver VOD
SN65HVD230
SN65HVD231
SN65HVD232
SLOS346G – MARCH 2001 – REVISED JUNE 2002
10 www.ti.com
PARAMETER MEASUREMENT INFORMATION
≈ 2.3 V
Dominant
Recessive
CANL
VOL
≈ 3 V VOH
≈ 1 V VOH
CANH CANH
CANL
Figure 3. Driver Output Voltage Definitions
RL = 60 Ω VO
50 Ω
Signal
Generator
(see Note A)
CL = 50 pF
(see Note B)
90%
Output
0.9 V
10%
tf
VOD(R)
VOD(D)
tr
Input
0 V
3 V
tPHL
1.5 V
tPLH
RS = 0 Ω to 100 kΩ for SN65HVD230 and SN65HVD231
N/A for SN65HVD232
0.5 V
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 500 kHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
Zo = 50 Ω.
B. CL includes probe and jig capacitance.
Figure 4. Driver Test Circuit and Voltage Waveforms
VIC
VCANHVCANL
2
VID
VO
VCANL
VCANH
IO
Figure 5. Receiver Voltage and Current Definitions
SN65HVD230
SN65HVD231
SN65HVD232
SLOS346G – MARCH 2001 – REVISED JUNE 2002
www.ti.com 11
PARAMETER MEASUREMENT INFORMATION
50 Ω
Signal
Generator
(see Note A) CL = 15 pF
(see Note B)
1.5 V
90%
Output 1.3 V
10%
tf
VOL
VOH
tr
Input
1.5 V
2.9 V
tPHL
2.2 V
tPLH
Output
NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 500 kHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns,
Zo = 50 Ω.
B. CL includes probe and jig capacitance.
Figure 6. Receiver Test Circuit and Voltage Waveforms
100 Ω
Pulse Generator,
15 μs Duration,
1% Duty Cycle
Figure 7. Overvoltage Protection
SN65HVD230
SN65HVD231
SN65HVD232
SLOS346G – MARCH 2001 – REVISED JUNE 2002
12 www.ti.com
PARAMETER MEASUREMENT INFORMATION
Table 1. Receiver Characteristics Over Common Mode With V(Rs) = 1.2 V
VIC VID VCANH VCANL R OUTPUT
–2 V 900 mV –1.55 V –2.45 V L
7 V 900 mV 8.45 V 6.55 V L
V
1 V 6 V 4 V –2 V L
VOL
4 V 6 V 7 V 1 V L
–2 V 500 mV –1.75 V –2.25 V H
7 V 500 mV 7.25 V 6.75 V H
1 V –6 V –2 V 4 V H VOH
4 V –6 V 1 V 7 V H
X X Open Open H
10 kΩ
0 V
CL = 15 pF
R Output 1.3 V
t(WAKE)
V(Rs) 1.5 V
50 Ω
Signal
Generator
Generator
PRR = 150 kHz
50% Duty Cycle
tr, tf < 6 ns
Zo = 50 Ω
V(Rs)
D
RS
R Output
VCC
0 V
VCC
60 Ω
+
–
Figure 8. t(WAKE) Test Circuit and Voltage Waveforms
SN65HVD230
SN65HVD231
SN65HVD232
SLOS346G – MARCH 2001 – REVISED JUNE 2002
www.ti.com 13
PARAMETER MEASUREMENT INFORMATION
50% 50%
50% 50%
D
VI
RS
R
DUT
CANH
CANL
60 Ω ±1%
15 pF ±20%
+
VO
0 Ω, 10 kΩ or
100 kΩ ±5%
t(LOOP2)
VI
VO
VCC
0 V
VOH
VOL
t(LOOP1)
Figure 9. t(LOOP) Test Circuit and Voltage Waveforms
NOTE: All VI input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 6 ns, Pulse Repetition Rate (PRR) = 125 kHz,
50% duty cycle
SN65HVD230
SN65HVD231
SN65HVD232
SLOS346G – MARCH 2001 – REVISED JUNE 2002
14 www.ti.com
TYPICAL CHARACTERISTICS
Figure 10
25
26
27
28
29
30
31
32
33
0 250 500 750 1000 1250 1500 1750 2000
– Supply Current (RMS) – mA
SUPPLY CURRENT (RMS)
vs
FREQUENCY
ICC
f – Frequency – kbps
Figure 11
–16
–14
–12
–10
–8
–6
–4
–2
0
0 0.6 1.1 1.6 2.1 2.6 3.1 3.6
LOGIC INPUT CURRENT (PIN D)
vs
INPUT VOLTAGE
II(L) – Logic Input Current – μA
VI – Input Voltage – V
Figure 12
–400
–300
–200
–100
0
100
200
300
400
–7 –6 –4 –3 –1 0 1 3 4 6 7 8 10 11 12
VCC = 0 V
VCC = 3.6 V
BUS INPUT CURRENT
vs
BUS INPUT VOLTAGE
II – Bus Input Current – μA
VI – Bus Input Voltage – V
Figure 13
0 1 2 3 4
DRIVER LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
IOL– Driver Low-Level Output Current – mA
VO(CANL)– Low-Level Output Voltage – V
0
20
40
60
80
100
120
140
160
SN65HVD230
SN65HVD231
SN65HVD232
SLOS346G – MARCH 2001 – REVISED JUNE 2002
www.ti.com 15
TYPICAL CHARACTERISTICS
Figure 14
0
20
40
60
80
100
120
0 0.5 1 1.5 2 2.5 3 3.5
– Driver High-Level Output Current – mA
DRIVER HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
VO(CANH) – High-Level Output Voltage – V
I OH
Figure 15
0
0.5
1
1.5
2
2.5
3
–55 –40 0 25 70 85 125
VCC = 3.6 V
VCC = 3.3 V
VCC = 3 V
DOMINANT VOLTAGE (VOD)
vs
FREE-AIR TEMPERATURE
VOD– Dominant Voltage – V
TA – Free-Air Temperature – °C
Figure 16
30
31
32
33
34
35
36
37
38
–55 –40 0 25 70 85 125
VCC = 3.3 V
VCC = 3 V
VCC = 3.6 V
RECEIVER LOW-TO-HIGH PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
RS = 0
tPLH – Receiver Low-to-High Propagation Delay Time – ns
TA – Free-Air Temperature – °C
Figure 17
VCC = 3.3 V
VCC = 3 V
VCC = 3.6 V
34
35
36
37
38
39
40
–55 –40 0 25 70 85 125
RS = 0
RECEIVER HIGH-TO-LOW PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
tPHL– Receiver High-to-Low Propagation Delay Time – ns
TA – Free-Air Temperature – °C
SN65HVD230
SN65HVD231
SN65HVD232
SLOS346G – MARCH 2001 – REVISED JUNE 2002
16 www.ti.com
TYPICAL CHARACTERISTICS
Figure 18
10
15
20
25
30
35
40
45
50
55
–55 –40 0 25 70 85 125
VCC = 3.3 V
VCC = 3 V
VCC = 3.6 V
RS = 0
DRIVER LOW-TO-HIGH PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
tPLH – Driver Low-to-High Propagation Delay Time – ns
TA – Free-Air Temperature – °C
Figure 19
50
55
60
65
70
75
80
85
90
–55 –40 0 25 70 85 125
VCC = 3.3 V
VCC = 3 V
VCC = 3.6 V
RS = 0
DRIVER HIGH-TO-LOW PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
tPHL– Driver High-to-Low Propagation Delay Time – ns
TA – Free-Air Temperature – °C
Figure 20
0
10
20
30
40
50
60
70
80
90
–55 –40 0 25 70 85 125
VCC = 3.3 V
VCC = 3 V
VCC = 3.6 V
RS = 10 kΩ
DRIVER LOW-TO-HIGH PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
tPLH – Driver Low-to-High Propagation Delay Time – ns
TA – Free-Air Temperature – °C
Figure 21
80
90
100
110
120
130
140
150
–55 –40 0 25 70 85 125
VCC = 3.3 V
VCC = 3 V
VCC = 3.6 V
RS = 10 kΩ
DRIVER HIGH-TO-LOW PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
tPHL – Driver High-to-Low Propagation Delay Time – ns
TA – Free-Air Temperature – °C
SN65HVD230
SN65HVD231
SN65HVD232
SLOS346G – MARCH 2001 – REVISED JUNE 2002
www.ti.com 17
TYPICAL CHARACTERISTICS
Figure 22
0
100
200
300
400
500
600
700
800
–55 –40 0 25 70 85 125
VCC = 3.3 V
VCC = 3 V
VCC = 3.6 V
RS = 100 kΩ
DRIVER LOW-TO-HIGH PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
tPLH – Driver Low-to-High Propagation Delay Time – ns
TA – Free-Air Temperature – °C
Figure 23
700
750
800
850
900
950
1000
–55 –40 0 25 70 85 125
VCC = 3.3 V
VCC = 3 V
VCC = 3.6 V
RS = 100 kΩ
DRIVER HIGH-TO-LOW PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
tPHL– Driver High-to-Low Propagation Delay Time – ns
TA – Free-Air Temperature – °C
Figure 24
0
10
20
30
40
50
1 1.5 2 2.5 3 3.5 4
DRIVER OUTPUT CURRENT
vs
SUPPLY VOLTAGE
IO – Driver Output Current – mA
VCC – Supply Voltage – V
Figure 25
0
0.10
0.20
0.30
0.40
0.50
0.60
0.70
0.80
0.90
1.00
1.10
1.20
1.30
1.40
0 50 100 150 200
1.50
VCC = 3.3 V
VCC = 3 V
VCC = 3.6 V
DIFFERENTIAL DRIVER OUTPUT FALL TIME
vs
SOURCE RESISTANCE (Rs)
tf – Differential Driver Output Fall Time – μ s
Rs – Source Resistance – kΩ
SN65HVD230
SN65HVD231
SN65HVD232
SLOS346G – MARCH 2001 – REVISED JUNE 2002
18 www.ti.com
TYPICAL CHARACTERISTICS
Figure 26
0
0.5
1
1.5
2
2.5
3
–50 –5 5 50
VCC = 3 V
VCC = 3.6 V
REFERENCE VOLTAGE
vs
REFERENCE CURRENT
Vref – Reference Voltage – V
Iref – Reference Current – μA
APPLICATION INFORMATION
This application provides information concerning the implementation of the physical medium attachment layer
in a CAN network according to the ISO 11898 standard. It presents a typical application circuit and test results,
as well as discussions on slope control, total loop delay, and interoperability in 5-V systems.
introduction
ISO 11898 is the international standard for high-speed serial communication using the controller area network
(CAN) bus protocol. It supports multimaster operation, real-time control, programmable data rates up to 1 Mbps,
and powerful redundant error checking procedures that provide reliable data transmission. It is suited for
networking intelligent devices as well as sensors and actuators within the rugged electrical environment of a
machine chassis or factory floor. The SN65HVD230 family of 3.3-V CAN transceivers implement the lowest
layers of the ISO/OSI reference model. This is the interface with the physical signaling output of the CAN
controller of the Texas Instruments TMS320Lx240x 3.3–V DSPs, as illustrated in Figure 27.
SN65HVD230
SN65HVD231
SN65HVD232
SLOS346G – MARCH 2001 – REVISED JUNE 2002
www.ti.com 19
APPLICATION INFORMATION
TMS320Lx2403/6/7
3.3-V
DSP
ISO 11898 Specification Implementation
Application Specific Layer
Data-Link
Layer
Logic Link Control
Medium Access Control
Physical
Layer
Physical Signaling
Physical Medium Attachment
Medium Dependent Interface
Embedded
CAN
Controller
SN65HVD230
CAN Bus-Line
Figure 27. The Layered ISO 11898 Standard Architecture
The SN65HVD230 family of CAN transceivers are compatible with the ISO 11898 standard; this ensures
interoperability with other standard-compliant products.
application of the SN65HVD230
Figure 28 illustrates a typical application of the SN65HVD230 family. The output of a DSP’s CAN controller is
connected to the serial driver input, pin D, and receiver serial output, pin R, of the transceiver. The transceiver
is then attached to the differential bus lines at pins CANH and CANL. Typically, the bus is a twisted pair of wires
with a characteristic impedance of 120 Ω, in the standard half-duplex multipoint topology of Figure 29. Each end
of the bus is terminated with 120-Ω resistors in compliance with the standard to minimize signal reflections on
the bus.
SN65HVD230
SN65HVD231
SN65HVD232
SLOS346G – MARCH 2001 – REVISED JUNE 2002
20 www.ti.com
APPLICATION INFORMATION
TMS320Lx2403/6/7
CAN Bus Line
CAN-Controller
CANTX/IOPC6
SN65HVD230
Electronic Control Unit (ECU)
CANH CANL
D R
CANRX/IOPC7
Figure 28. Details of a Typical CAN Node
CANH
CANL
CAN Bus Line
ECU ECU ECU
1 2 n
120 Ω 120 Ω
Figure 29. Typical CAN Network
The SN65HVD230/231/232 3.3-V CAN transceivers provide the interface between the 3.3-V
TMS320Lx2403/6/7 CAN DSPs and the differential bus line, and are designed to transmit data at signaling rates
up to 1 Mbps as defined by the ISO 11898 standard.
features of the SN65HVD230, SN65HVD231, and SN65HVD232
The SN65HVD230/231/232 are pin-compatible (but not functionally identical) with one another and, depending
upon the application, may be used with identical circuit boards.
These transceivers feature 3.3-V operation and standard compatibility with signaling rates up to 1 Mbps, and
also offer 16-kV HBM ESD protection on the bus pins, thermal shutdown protection, bus fault protection, and
open-circuit receiver failsafe. The fail-safe design of the receiver assures a logic high at the receiver output if
the bus wires become open circuited. If a high ambient operating environment temperature or excessive output
current result in thermal shutdown, the bus pins become high impedance, while the D and R pins default to a
logic high.
SN65HVD230
SN65HVD231
SN65HVD232
SLOS346G – MARCH 2001 – REVISED JUNE 2002
www.ti.com 21
APPLICATION INFORMATION
features of the SN65HVD230, SN65HVD231, and SN65HVD232 (continued)
The bus pins are also maintained in a high-impedance state during low VCC conditions to ensure glitch-free
power-up and power-down bus protection for hot-plugging applications. This high-impedance condition also
means that an unpowered node does not disturb the bus. Transceivers without this feature usually have a very
low output impedance. This results in a high current demand when the transceiver is unpowered, a condition
that could affect the entire bus.
operating modes
RS (pin 8) of the SN65HVD230 and SN65HVD231 provides for three different modes of operation: high-speed
mode, slope-control mode, and low-power mode.
high-speed
The high-speed mode can be selected by applying a logic low to RS (pin 8). The high-speed mode of operation
is commonly employed in industrial applications. High-speed allows the output to switch as fast as possible with
no internal limitation on the output rise and fall slopes. The only limitations of the high-speed operation are cable
length and radiated emission concerns, each of which is addressed by the slope control mode of operation.
If the low-power standby mode is to be employed in the circuit, direct connection to a DSP output pin can be
used to switch between a logic-low level (< 1 V) for high speed operation, and the logic-high level (> 0.75 VCC)
for standby. Figure 30 shows a typical DSP connection, and Figure 31 shows the HVD230 driver output signal
in high-speed mode on the CAN bus.
TMS320LF2406
or
TMS320LF2407
IOPF6
1
2
3
4
8
7
6
5
D
GND
VCC
R
CANH
CANL
Vref
RS
Figure 30. RS (Pin 8) Connection to a TMS320LF2406/07 for High Speed/Standby Operation
SN65HVD230
SN65HVD231
SN65HVD232
SLOS346G – MARCH 2001 – REVISED JUNE 2002
22 www.ti.com
APPLICATION INFORMATION
high-speed (continued)
1
1 Mbps
Driver Output
NRZ Data
Figure 31. Typical High Speed SN65HVD230 Output Waveform Into a 60-Ω Load
slope control
Electromagnetic compatibility is essential in many applications using unshielded bus cable to reduce system
cost. To reduce the electromagnetic interference generated by fast rise times and resulting harmonics, the rise
and fall slopes of the SN65HVD230 and SN65HVD231 driver outputs can be adjusted by connecting a resistor
from RS (pin 8) to ground or to a logic low voltage, as shown in Figure 32. The slope of the driver output signal
is proportional to the pin’s output current. This slope control is implemented with an external resistor value of
10 kΩ to achieve a ≈ 15 V/μs slew rate, and up to 100 kΩ to achieve a ≈ 2.0 V/μs slew rate as displayed in
Figure 33. Typical driver output waveforms from a pulse input signal with and without slope control are displayed
in Figure 34. A pulse input is used rather than NRZ data to clearly display the actual slew rate.
TMS320LF2406
or
TMS320LF2407
IOPF6
1
2
3
4
8
7
6
5
D
GND
VCC
R
CANH
CANL
Vref
10 kΩ
to
RS 100 kΩ
Figure 32. Slope Control/Standby Connection to a DSP
SN65HVD230
SN65HVD231
SN65HVD232
SLOS346G – MARCH 2001 – REVISED JUNE 2002
www.ti.com 23
APPLICATION INFORMATION
Slope Control Resistance – kΩ
0
5
10
15
20
25
0 10 20 30 40 50 60 70 80 90
DRIVER OUTPUT SIGNAL SLOPE
vs
SLOPE CONTROL RESISTANCE
4.7 6.8 10 15 22 33 47 68 100
Driver Outout Signal Slop – V/μ s
Figure 33. HVD230 Driver Output Signal Slope vs Slope Control Resistance Value
RS = 0 Ω
RS = 10 kΩ
RS = 100 kΩ
Figure 34. Typical SN65HVD230 250-kbps Output Pulse Waveforms With Slope Control
SN65HVD230
SN65HVD231
SN65HVD232
SLOS346G – MARCH 2001 – REVISED JUNE 2002
24 www.ti.com
APPLICATION INFORMATION
standby mode (listen only mode) of the HVD230
If a logic high (> 0.75 VCC) is applied to RS (pin 8) in Figures 30 and 32, the circuit of the SN65HVD230 enters
a low-current, listen only standby mode, during which the driver is switched off and the receiver remains active.
In this listen only state, the transceiver is completely passive to the bus. It makes no difference if a slope control
resistor is in place as shown in Figure 32. The DSP can reverse this low-power standby mode when the rising
edge of a dominant state (bus differential voltage > 900 mV typical) occurs on the bus. The DSP, sensing bus
activity, reactivates the driver circuit by placing a logic low (< 1.2 V) on RS (pin 8).
the babbling idiot protection of the HVD230
Occasionally, a runaway CAN controller unintentionally sends messages that completely tie up the bus (what
is referred to in CAN jargon as a babbling idiot). When this occurs, the DSP can engage the listen-only standby
mode to disengage the driver and release the bus, even when access to the CAN controller has been lost. When
the driver circuit is deactivated, its outputs default to a high-impedance state.
sleep mode of the HVD231
The unique difference between the SN65HVD230 and the SN65HVD231 is that both driver and receiver are
switched off in the SN65HVD231 when a logic high is applied to RS (pin 8). The device remains in a very low
power-sleep mode until the circuit is reactivated with a logic low applied to RS (pin 8). While in this sleep mode,
the bus-pins are in a high-impedance state, while the D and R pins default to a logic high.
loop propagation delay
Transceiver loop delay is a measure of the overall device propagation delay, consisting of the delay from the
driver input to the differential outputs, plus the delay from the receiver inputs to its output.
The loop delay of the transceiver displayed in Figure 35 increases accordingly when slope control is being used.
This increased loop delay means that the total bus length must be reduced to meet the CAN bit-timing
requirements of the overall system. The loop delay becomes ≈100 ns when employing slope control with a
10-kΩ resistor, and ≈500 ns with a 100-kΩ resistor. Therefore, considering that the rule-of-thumb propagation
delay of typical bus cable is 5 ns/m, slope control with the 100-kΩ resistor decreases the allowable bus length
by the difference between the 500-ns max loop delay and the loop delay with no slope control, 70.7 ns. This
equates to (500–70.7 ns)/5 ns, or approximately 86 m less bus length. This slew-rate/bus length trade-off to
reduce electromagnetic interference to adjoining circuits from the bus can also be solved with a quality shielded
bus cable.
SN65HVD230
SN65HVD231
SN65HVD232
SLOS346G – MARCH 2001 – REVISED JUNE 2002
www.ti.com 25
APPLICATION INFORMATION
( )
Figure 35. 70.7-ns Loop Delay Through the HVD230 With RS = 0
SN65HVD230
SN65HVD231
SN65HVD232
SLOS346G – MARCH 2001 – REVISED JUNE 2002
26 www.ti.com
APPLICATION INFORMATION
interoperability with 5-V CAN systems
It is essential that the 3.3-V HVD230 family performs seamlessly with 5-V transceivers because of the large
number of 5-V devices installed. Figure 36 displays a test bus of a 3.3-V node with the HVD230, and three 5-V
nodes: one for each of TI’s SN65LBC031 and UC5350 transceivers, and one using a competitor X250
transceiver.
SN65HVD230
Tektronix
HFS–9003
Pattern
Generator
Tektronix
784D
Trigger Oscilloscope
Input
One Meter Belden Cable #82841
SN65LBC031 UC5350 Competitor X250
HP E3516A
3.3-V Power
Supply
HP E3516A
5-V Power
Supply
Tektronix
P6243
Single-Ended
Probes
120 Ω 120 Ω
Figure 36. 3.3-V/5-V CAN Transceiver Test Bed
SN65HVD230
SN65HVD231
SN65HVD232
SLOS346G – MARCH 2001 – REVISED JUNE 2002
www.ti.com 27
APPLICATION INFORMATION
Driver
Input
CAN
Bus
Receiver
Output
Figure 37. The HVD230’s Input, CAN Bus, and X250’s RXD Output Waveforms
Figure 37 displays the HVD230’s input signal, the CAN bus, and the competitor X250’s receiver output
waveforms. The input waveform from the Tektronix HFS-9003 Pattern Generator in Figure 36 to the HVD230
is a 250-kbps pulse for this test. The circuit is monitored with Tektronix P6243, 1-GHz single-ended probes in
order to display the CAN dominant and recessive bus states.
Figure 37 displays the 250-kbps pulse input waveform to the HVD230 on channel 1. Channels 2 and 3 display
CANH and CANL respectively, with their recessive bus states overlaying each other to clearly display the
dominant and recessive CAN bus states. Channel 4 is the receiver output waveform of the competitor X250.
SN65HVD230
SN65HVD231
SN65HVD232
SLOS346G – MARCH 2001 – REVISED JUNE 2002
28 www.ti.com
MECHANICAL DATA
D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
4040047/D 10/96
0.228 (5,80)
0.244 (6,20)
0.069 (1,75) MAX
0.010 (0,25)
0.004 (0,10)
1
14
0.014 (0,35)
0.020 (0,51)
A
0.157 (4,00)
0.150 (3,81)
7
8
0.044 (1,12)
0.016 (0,40)
Seating Plane
0.010 (0,25)
PINS **
0.008 (0,20) NOM
A MIN
A MAX
DIM
Gage Plane
0.189
(4,80)
(5,00)
0.197
8
(8,55)
(8,75)
0.337
14
0.344
(9,80)
16
0.394
(10,00)
0.386
0.004 (0,10)
0.010 (0,25) M
0.050 (1,27)
0°–8°
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012
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